[SOLVED] How to handle i2c clock domain to system clock domain?

[u24c02]

Hi i have some questuon about i2c clock domain switching to system clock
Currentlly, i use AHB lite system and i'm trying to add i2c slave in AHB Lite system.
Here is question.

How can i handle i2c scl clock between AHBsystem's clock domain ?
especially, i willing to move date from i2c to ahb lite system data bus
So, how can i get safefully data from i2c to system ahb lite system without cdc problems?

Especially, what is espectate in verilog rtl design?

 

[barry]

I don't know anything about AHB, but I think you've got two different serial protocols, right? But you're writing something in verilog; is there an FPGA or CPLD in here somewhere?

If you ARE, in fact, using an FPGA, the simplest solution would be to use a fifo between the two clock domains.

I think we need more information.

 

[u24c02]

i simply abbreviate this problems.

info)
i) i'll make i2c slave rtl block in the system not master.
ii) the system have AHB bus system.
iii) AHB is working HCLK ( BUS clock) but i2c is not decision yet.

here is my question.

When i make such as following what happen problem occur in circumstance?

1.i'll make such as OPENCORES' i2c rtl design (OPENCORES i2c using only 2 port scl, sda)
Also i'll make interface I2C to AHB bus(HCLK).
Is there any problems in circumstance like setup and hold violation and interface I2C to AHB bus.

For safe-fully,how i make I2C slave block for interface AHB BUS?
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what happen problem occur in circumstance

 

[sakthikumaran87]

you have to apply CDC synchronizers between the two domains.

 

[u24c02]

you have to apply CDC synchronizers between the two domains.

How can i best cdc do?

 

[FvM]

What do you exactly mean with I2C clock domain? I2C is essentially an asynchronous protocol and it's slow. The most reasonable way to design an I2C slave in a system that provides a system clock is to process the I2C signals in the system clock domain. So there won't be but a rather trivial problem of synchronizing SDA and SCL to the system clock.

 

[u24c02]

What do you exactly mean with I2C clock domain? I2C is essentially an asynchronous protocol and it's slow. The most reasonable way to design an I2C slave in a system that provides a system clock is to process the I2C signals in the system clock domain. So there won't be but a rather trivial problem of synchronizing SDA and SCL to the system clock.

I know i2c is very slow protocol but i need to know that how can i design sda, scl support for 0 hold time?

 

[FvM]

how can i design sda, scl support for 0 hold time

Don't know what you exactly mean with 0 hold time related to I2C? A FPGA slave is expected to keep the I2C specification, that leaves plenty of room for synchronous processing of SDA and SCL.

 

[barry]

Could you explain this a little clearer? It SOUNDS like you are trying to make an I2C receiver work with an AHB bus. I don't know what you mean by statements like "Is there any problems in circumstance like setup and hold violation and interface I2C to AHB bus."

 

[u24c02]

Could you explain this a little clearer? It SOUNDS like you are trying to make an I2C receiver work with an AHB bus. I don't know what you mean by statements like "Is there any problems in circumstance like setup and hold violation and interface I2C to AHB bus."

Yes, i'm making I2C slave block by verilog into AHB Bus system.
Also, "Is there any problems in circumstance like setup and hold violation and interface I2C to AHB bus"
In other words, When i make I2C slave block by verilog, what am i consider fact in timing close to I2C & AHB bus interfaces?

Did you understand?

 

[barry]

The fact that you're creating a block in verilog (or VHDL or whatever) is irrelevant. Timing closure has to do with the actual hardware that is implemented from your code. As I said in a previous post, I'm unfamiliar with the AHB bus, but it's still not clear if you are trying to create a block that will translate the I2C protocol to the AHB protocol, or force the I2C receiver to work directly with the AHB bus. Regardless, if the two busses are asynchronous you will need to to implement some synchronizers between the two busses.

 

[FvM]

AHB is a synchronous bus with sufficient high clock rate. Running the I2C interface with the same clock seems easy and straightforward. However, if you like it complicated, you can use unrelated clocks and utilize synchronizers.

 

[u24c02]

The fact that you're creating a block in verilog (or VHDL or whatever) is irrelevant. Timing closure has to do with the actual hardware that is implemented from your code. As I said in a previous post, I'm unfamiliar with the AHB bus, but it's still not clear if you are trying to create a block that will translate the I2C protocol to the AHB protocol, or force the I2C receiver to work directly with the AHB bus. Regardless, if the two busses are asynchronous you will need to to implement some synchronizers between the two busses.

hmm, i miss one thing.
AHB Bus clock is variable clock by PLL.
Of course, I2C clock is more slow than AHB BUS clock.
But, what if there is any some occur event of setup or hold violation between AHB bus clock and i2c clock interfaces?

 

[morris_mano]

If you are trying to read/write AHB slave through I2c, here is what you need. You need I2C slave that will talk to I2C host, then you need logic to convert I2C signals to AHB master signals that will read/write to AHB slave(registers). To do this, you need to synchronize all i2c signals before you use those signals to convert to AHB master signals to prevent metastability.