how to give values in uart transmitter

[sreelatha219]

how to give values to uart transmitter so that i can those values in pc.
nd this is my code
module uart_tx(
input clk,
input reset,
input transmit,
input [7:0] data,
output reg Txd
);
reg [3:0] bitcounter;
reg [12:0]counter;

reg state,nextstate;

reg[10:0]rightshiftreg; //start,8 bit data,stop bits

reg shift,load,clear;





always@(posedge clk)

begin
if(reset) begin
state<=0;
counter<=0;
bitcounter<=0;
end
else begin
counter<=counter+1;
if(counter>=1)
begin
state<=nextstate;
counter<=0;
if(load) rightshiftreg<={1'b1,^data,data,1'b0};
if(clear) bitcounter<=0;
if(shift) begin
rightshiftreg<=rightshiftreg>>1;
bitcounter<=bitcounter+1;
end
end
end
end

always@(state or bitcounter or transmit)
begin
load<=0;
shift<=0;
clear<=0;
Txd<=1;
case(state)
0:begin
if(transmit==1)
begin
nextstate<=1;
load<=1;
shift<=0;
clear<=0;
end
else begin
nextstate<=0;
Txd<=1;
end

end

1:begin
if(bitcounter<=10) begin
nextstate<=0;
clear<=1;
end
else begin
nextstate<=1;
shift<=1;
Txd<=rightshiftreg[0];
end

end
endcase

end

endmodule

 

[cvc]

Write a Testbench in Verilog. Sample code:

module uart_tx_tb;

  reg clk, reset,transmit;
  reg   [7:0] data,
    wire Txd;

   uart_tx dut (.*); // SystemVerilog syntax

  // generate clk - left as exercise for you..

  // Used SystemVerilog code, if your tool dosn't support, change it/comment it,
  // use plain Verilog  or even better try out SV tool such as Riviera-Pro (aldec.com)

  default clocking @(posedge clk);
  endclocking

  initial begin : stim
    ##10;
    reset = 0;
    data = $random;
    transmit = 1;
    ##8 transmit = 0;
   ##10 $finish;
  end : stim

endmodule : uart_tx_tb

HTH
TeamCVC
www.cvcblr.com/blog

 

[sreelatha219]

how to give values to uart transmitter so that i can those values in pc.
nd this is my code
module uart_tx(
input clk,
input reset,
input transmit,
input [7:0] data,
output reg Txd
);
reg [3:0] bitcounter;
reg [12:0]counter;

reg state,nextstate;

reg[10:0]rightshiftreg; //start,8 bit data,stop bits

reg shift,load,clear;





always@(posedge clk)

begin
if(reset) begin
state<=0;
counter<=0;
bitcounter<=0;
end
else begin
counter<=counter+1;
if(counter>=1)
begin
state<=nextstate;
counter<=0;
if(load) rightshiftreg<={1'b1,^data,data,1'b0};
if(clear) bitcounter<=0;
if(shift) begin
rightshiftreg<=rightshiftreg>>1;
bitcounter<=bitcounter+1;
end
end
end
end

always@(state or bitcounter or transmit)
begin
load<=0;
shift<=0;
clear<=0;
Txd<=1;
case(state)
0:begin
if(transmit==1)
begin
nextstate<=1;
load<=1;
shift<=0;
clear<=0;
end
else begin
nextstate<=0;
Txd<=1;
end

end

1:begin
if(bitcounter<=10) begin
nextstate<=0;
clear<=1;
end
else begin
nextstate<=1;
shift<=1;
Txd<=rightshiftreg[0];
end

end
endcase

end

endmodule

thanks for the reply ...
it was working fine in simulator.
but i want to send some data from transmitter.so that i can see the sent data on pc hyper terminal.
i donot understand how to send data from transmitter.should i initialize the value in the code it self?