How to get the capacitance from a design in Altera FPGA

[gillianomenezes]

Hi,

I'm trying to get the capacitance for every resource in a FPGA (altera) design. Some people told me to use HSPICE to get the capacitance table from the design. So I configured quartus to write some ".sp" files and uses it as input files in HSPICE tool. But, I don't understand what the output file says. This is the output file: View attachment HSPICE_output.lis.txt. I need to know how to get the capacitance for every resource used by the design in the FPGA.

Thanks in advance for your help!

 

[marce]

What are you going to use these capacitances for?
Do you mean the capacitance from the device pin to the die?
If so IBIS data may be what you want...

 

[FvM]

Apparently, he's behind the internal power dissipation capacitances of the design. Honestly, I don't know if Altera's HSPICE libraries are modelling them somehow. But you should be able to determine this by setting up test designs with different amount of toggling registers and LEs and compare the core supply current. However, if the HSPICE libraries aren't explicitely said to model internal behaviour on a transistor level (are they?) or to provide functional equivalence in certain regard, I won't expect correct modelling of power dissipation capacitances.

 

[gillianomenezes]

What are you going to use these capacitances for?
Do you mean the capacitance from the device pin to the die?
If so IBIS data may be what you want...

I want the device total capacitance to estimate power dissipation.

---------- Post added at 14:43 ---------- Previous post was at 14:00 ----------

Apparently, he's behind the internal power dissipation capacitances of the design. Honestly, I don't know if Altera's HSPICE libraries are modelling them somehow. But you should be able to determine this by setting up test designs with different amount of toggling registers and LEs and compare the core supply current. However, if the HSPICE libraries aren't explicitely said to model internal behaviour on a transistor level (are they?) or to provide functional equivalence in certain regard, I won't expect correct modelling of power dissipation capacitances.

How can I set up the toggling registers and LEs for a test design to verify if the Altera's HSPICE are modelling the internal power dissipation capacitances?