How to get parallel hardware in simulation using case statment?

[bharat_in]

Till now, i was under impression that case statment will generate non-priority encoder hardware both in simulation and synthesis, but following coding shows that in simulation in works like proirity encoder... :-(

module m ();

wire [3:0] w1 = 4'b1101 ;

initial
begin
#4;
case(1'b1)
w1[0]: $display("0") ;
w1[1]: $display("1") ;
w1[2]: $display("2") ;
w1[3]: $display("3") ;
default: $display("Default") ;
endcase
end

endmodule

Output:
0

I guess, in this case it will have pre-synthesis and post-synthesis simulation mismatch.
Can anyone please explain, how to get parallel hardware in simulation using case statment?

 

[nikhilindia85]

case statement

initial will be ignored by synthesis tool and display also not synthesizble
try to write synthesizable rtl code

 

[fm_com_28]

Re: case statement

What I know is that in VHDL, case statement is a sequential statement not a concurrent, is this the situation for Verilog?

 

[pinnacle.chip]

Re: case statement

When u r talking about synthesis then #4 and $display should not be there in ur RTL.
After u have rectified this, u have should add parallel_case directive specifically for this condition as choice of case statement is variable here. write like this:

case(1'b1) //synopsis parallel_case
w1[0]:
-----
-----

 

[cherjier]

case statement

copy your code here:
case(1'b1)
w1[0]: $display("0") ;
w1[1]: $display("1") ;
w1[2]: $display("2") ;

i think is ur case condition have some issue.
u try the case statement as follow:

case(w1) //<- here should be w1, not 1'b1
w1[0]: $display("0") ;
w1[1]: $display("1") ;
w1[2]: $display("2") ;

 

[foster_cn]

case statement

have you tried with synthesis directive on those

 

[bharat_in]

Re: case statement

for those who were asking for synthesizable module....

module m1(w1,a,y);

input wire [3:0] w1;
input wire [3:0] a ;
output reg y;

always @ *
begin
  case(1'b1) 
    w1[0]: y = a[0];
    w1[1]: y = a[1];
    w1[2]: y = a[2];
    w1[3]: y = a[3];
    default: y = 0;
  endcase
end  

endmodule

for w1 = 4'b1001 and a = 4'b0001. In simulation Y evaluates to 1'b1 as w1[0] is 1'b1 and it is having higher priority than others.

Now may question is, if i want to create parallel case in simulation that how can i create it. For synthesis i can specify parallel case directive, but then i will have post-synthesis and pre-synthesis simulation mismatch....

 

[shiv_emf]

case statement

U can use constraint to avoid mismatches

 

[bharat_in]

Re: case statement

@shiv_emf
Please, tell me what kind of constrains should i use, in that case?

 

[avimit]

Re: case statement

Hi bharat_in,
Let me look at the problem from a straight fwd perspective.
One output Y, may get a value from either of 4 inputs a0, a1, a2, a3,
depending upon 4 other inputs w0, w1, w2 ,w3. OK?

ok 4to1 mux, but you have 4 lines to select(instead 2, which you normally have), i.e 16 input combinations to decide 4 choices for y i.e a0, a1, a2, a3?
4 choices aur 16 select combinations, bahut beinsaafi hai ye

So to have an exact sim/syn match, you may want to re-write your case statement as

case w1
  4'b0001 :
  4'b0010 :
  4'b0011 :
  4'b0100 :
  .
  .
  4'b1110 :
  4'b1111 :
  default y = 0;
endcase

you decide under these 16 cirumstances clearly, what Y should get.
This is an absolutely parallel code, with no amiguity, and no sim/syn mismatches.

coding it in a way you have done, is technically correct, but is not very explicit, as to what exactly you are after.
Kr,
Avi
http://www.vlsiip.com

 

[nand_gates]

Re: case statement

This is the way !
Hope this helps!

module m1(w1,a,y); 
input  [3:0] w1; 
input  [3:0] a ; 
output y; 
       assign y = (a[0] & w[0]) | (a[1] & w[1]) | (a[2] & w[2]) | (a[3] & w[3]);
endmodule