how to get correct extracted view in ic5033

[dragonwell]

Hi,

I want to creat a 3-input pseudo nor gate by using the sample gpdk lib, in order to get min size, I draw the layout myself, however the extracted nmos are in series, they should be in parallel. Besides to draw the individual transistors, how can I get the correct connection?

THX!

Piers

 

[flyankh]

Hi dragonwell

As I know,the 3-input pseudo nor gate have 3 PMOS at least,why do you only have one?Because I have no EDA tools in my PC,so I draw one in paint pad for you


flyankh

 

[dragonwell]

Thanks, Flyankh,

Well, I learn from text book that the pseudo mos has only one pmos as active load so that the configuration can be less complex. & transistors. As I understand, if use 3 pmos & 3 nmos that will form a 3-input cmos nor gate.

By the way, i can't find the attachment???

thx!

 

[flyankh]

Hi dragonwell

I feel that your pseudo nor gate have some fault---
the PMOS always turn on,so the output is always high.The gate can only output high signal whatever the input is.I am confused....

flyankh

 

[dragonwell]

Hi flyankh,

yes, the pmos always turns on so that the output will depends on the input of nmos, eithe one input "1" output will be "0", only all input are "0" output will be "1"

 

[flyankh]

Hi dragonwell

I understand your circuit now
But I want to know that how do you find the NMOS are in series?In LVS?And which tools are you using to check it?Maybe there are some mistake in using it,I can comfirm your NMOS are 100% in parallel

By the way,can you post your layout without the circuit?It will looks more cleaning

flyankh

 

[dragonwell]

Hi flyankh,

yes, i made a mistake on the nets, it has successful passed LVS. Thanks duke!