module div_2by3(/*AUTOARG*/
// Outputs
clk_2by3,
// Inputs
clk, reset_n
);
input clk, reset_n;
output clk_2by3;
reg [1:0] clk_by3_pos, clk_by3_neg ;
assign clk_2by3 = (~clk_by3_neg[0] & clk_by3_pos[0]) | (clk_by3_neg[1] & clk_by3_pos[1]);
always @(posedge clk or negedge reset_n)
if (!reset_n)
clk_by3_pos <= 0;
else
if (clk_by3_pos == 2)
clk_by3_pos <= 0;
else
clk_by3_pos <= clk_by3_pos + 1;
always @(negedge clk or negedge reset_n)
if (!reset_n)
clk_by3_neg <= 0;
else
if (clk_by3_neg == 2)
clk_by3_neg <= 0;
else
clk_by3_neg <= clk_by3_neg + 1;
endmodule // div_2by3