How to genetate a jittery clock in VHDL?

[pd]

Hi,
I want to create a clock for simulating my system across jittery clock ,which would be jittery (with mean of periodic jitter 0 and variance = 5ps).How can I introduce that clock?
Also I want the setup time of the flops to be a random number with some mean and variance.Can I create that type of flop?
Thanks in advance,
pd

 

[wice]

it can be difficult to genetate the signals with vhdl
but maybe it can be a little easier if you use verilog hdl,as there is a randm function in verilog hdl

 

[aji_vlsi]

Hi,
I want to create a clock for simulating my system across jittery clock ,which would be jittery (with mean of periodic jitter 0 and variance = 5ps).How can I introduce that clock?
Also I want the setup time of the flops to be a random number with some mean and variance.Can I create that type of flop?
Thanks in advance,
pd

You can use IEEE.MATH_REAL package to generate random number and achieve both these in VHDL.

Ajeetha, CVC
www.noveldv.com

 

[thomas18]

I use Matlab to generate the clock for system design.
Use Verilog-HDL to generate the jitter clock for RTL simulation.