how to generate test pattern atpg in tetramax

[avinashch]

i am trying to generate test pattern for the full adder but i am not getting anything out of it. it is reading the netlist but not giving any results.
it is giving N5 warning.
at the end of reading the netlist it gives
#modules=0, top-full_adder, #lines=29, cpu time=0.00 sec, memory= 0mb

is there anything else that i need to do to make it work??

here is my code for the adder:



module full_adder(input1,input2,carry_in,sum,carry_out);
input input1;
input input2;
input carry_in;
output sum;
output carry_out;

wire int1_sig;
wire int2_sig;
wire int3_sig;

assign int1_sig = input1 ^ input2;
assign int2_sig = input1 & input2;
assign sum = int1_sig ^ carry_in;
assign int3_sig = int1_sig & carry_in;
assign carry_out = int2_sig | int3_sig;

endmodule



the testbench is as follows:

module test_adder_1bit;

// Inputs
reg input1;
reg input2;
reg carry_in;

// Outputs
wire sum;
wire carry_out;

// Instantiate the Unit Under Test (UUT)
full_adder uut (
.input1(input1),
.input2(input2),
.carry_in(carry_in),
.sum(sum),
.carry_out(carry_out)
);

initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
carry_in = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

input1=1'b0;input2=1'b0;carry_in=1'b1;
#10;

input1=1'b0;input2=1'b1;carry_in=1'b0;
#10;
input1=1'b0;input2=1'b1;carry_in=1'b1;
#10;
input1=1'b1;input2=1'b0;carry_in=1'b0;
#10;
input1=1'b1;input2=1'b0;carry_in=1'b1;
#10;
input1=1'b1;input2=1'b1;carry_in=1'b0;
#10;
input1=1'b1;input2=1'b1;carry_in=1'b1;
end

endmodule

 

[jpvSoccer]

Hi, have you tried a gate-level netlist?

 

[avinashch]

no i havnt. i donno much about it.

 

[jducluzeau]

you must have a gate netlist to generate ATPG patterns.
Currently, Tetramax reads your code and doesn't see any scan Flip Flop then it generates nothing.

Regards,
Jerome

 

[avinashch]

i tried it using a gate netlist but still it is not giving me anything. do i need to add some other things to my code. i tried a simple gate netlist as follows:

module circuit(a,b,c,f);
input a,b,c;
output f;
wire d,e;
and and1(d,a,b);
and and2(e,b,c);
or or1(f,d,e);
endmodule

but it still gives me the same results.

 

[jducluzeau]

There is no Flip flop in your code. This is only combinatorial.
To generate ATPG patterns you need at least two Flip Flop, one scan_en input too.

 

[avinashch]

how to do that?

 

[jducluzeau]

ok! you want to use Tetramax to generate ATPG patterns.
But do you know what does these patterns?

 

[avinashch]

well...these patterns r used to find the faults in a design as in hardware design

 

[ConradATPG]

ATPG patterns are used to ensure that the actual chips match the specification (netlist). That is to say they are applied by a tester to find chips with manufacturing defects.