how to generate ramp for slope compensation?

[eem2am]

I am doing an offline flyback SMPS, and using UC3843 PWM controller

On page 8 (bottom) of the UC3843 datasheet………..

http://focus.ti.com/lit/ds/symlink/uc3843.pdf

……….it says we should use the clock ramp to provide a ramp for slope compensation.

However, on page 5 of “Six common reasons for power supply instability” by Dr Ray Ridley it says…………..

“The solution to the current loop instability is well known—
add a compensating ramp. However, as shown above, it is
crucial that you don’t try to use the clock ramp signal to generate
this.”

Dr Ray Ridley’s article can be found on …….

**broken link removed**

….in “Articles” in the “System design” section

(Dr Ridley’s article is also here
http://www.21dianyuan.com/bbs/attachments/pdf/2008/07/16/1216185133487d832d335cc.pdf
)


So what do you think?

Do we use the clock to generate the ramp or not?

 

[dick_freebird]

The output switch node might be more appropriate. Not all clocks
can be counted on to have relevant phase and duty.

 

[FvM]

However, as shown above, it is crucial that you don’t try to use the clock ramp signal to generate this.

Do you agree, that the author has shown, that the suggested UC3843 slope compensation circuit shouldn't be used? I don't.