How to generate pesudo random sequence other than LFSR?

[kumar85sunil]

can anybody plz tell me how to generate pesudo random sequence others then LFSR:?:

 

[abhikohli]

random sequence

In which lang ? If u want for simulation & using verilog u can use $random etc function. Similar function r available in SV & SC etc (Can't be used in RTL)

 

[kumar85sunil]

Re: random sequence

thanks

what is sv i am working with vhdl can u tell me to generate random seq in vhdl

 

[abhikohli]

random sequence

VHDL does not support Random numbers as such. U've very limited options for random number generation in VHDL. (Perhaps the only feature where verilog scores over VHDL )

1) As u've mentioned, use a LFSR.
2) Use FLI to import random function from some other language.
3) Write some random number generation algorithm in VHDL. (I don't know any)
4) Use an algorithm written by someone else.

I belive option 4 sound most appropriate one. U can google around to find some.
A few good ones can be found at:

**broken link removed**
(A random num lib for VHDL)
**broken link removed**
(A generic lib also containing rand gen)

Hope that helps you.
BTW SV stands for System Verilog.