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How to generate .lib timing library for subblock given large scale hierarchical P&R?

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chris_li

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How to generate .lib timing library for subblock given large scale hierarchical P&R?

Hi Guys,

FE team have partitioned the design into several subblocks. BE team intend to harden them one by one and then do integration at top level.

Whereas, for each subblock, how to get .lib timing library like that of SRAM, which is generated by memory compiler?

Any documentation can reference? Thanks in advance.
 
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