how to generate control signals

[Ravinder487]

Hi all,
I want generate 2 signals one with 700pS pulse width and 2nS pulse period signal and other with 710pS delay,300pS pulse width and 2nS pulse period.
And I want some signals to be delayed precisely by around 100-200pS.How can I do these things.I'm working with clock of 166p pulse width and 333pS pulse period.

 

[deepak488]

You cannot precisely generate signals with 700ps On period.......That ON period varies across corners........if u dont want that variation u may need to have clocks with factors of 700ps.......

generating delay between 100ps -200ps is some what easy compared to the above control signal generation..........use 4 binary signals as control signals as input to the block which generates delay according to the binary data given by you..........
that block is a combination of inverters and pass gates in parallel...this strucure is repeated 4 times( one for each binary bit)...these pass gates are ON depending on the binary inputs........if the binary input is 1001, then the 2nd and 3rd pass gatesare ON skipping the inverter path...........hence the effective delay of the block is first inverter and last inverter and the 2 pass gates delay...........


another simple way to generate 100- 200ps delay is cascade of inverters..........but that depends on technology........because variation of inverter delay between slow corner and fast corner is more in shorter channels........

in slow corner series of 8 inverters wiil give a delay of >200ps...............in fast corner it may give <80ps ........
if ur technology is .13 or .25 then u can easily do it with the series of inverters.........

 

[Ravinder487]

Thanks Deepak,
I don't want a very precice ON period for my control signal, a variation of 100ps in ON period of period doesn't deteriorate my ADC functioning but my requirement is to generate a control signal with On period of around 600-800ps and I've only one clock of 3Ghz frequency.

that block is a combination of inverters and pass gates in parallel...this strucure is repeated 4 times( one for each binary bit)...these pass gates are ON depending on the binary inputs........if the binary input is 1001, then the 2nd and 3rd pass gatesare ON skipping the inverter path...........hence the effective delay of the block is first inverter and last inverter and the 2 pass gates delay...........

Can you post sample schematic or sreenshot of circuit you speaking off
Thanks&Regards,
Ravinder.