how to generate a queue for checking asynchronous fifo

[sai685]

Actually for asychronous fifo if i want to compare the expected result with the produced result i need a queue . so i want to transfer the first input of my data_in into queue and later i compare the data_out and queue. so that it become first checker.
i want a code for that.

system verilog or if possible i want it in verilog

 

[sai685]

tell me whether this code is perfect for checking the asynchronous fifo by storing the value of data_in into a queue .

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Code Verilog - [expand]
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task queue;
  reg[31:0] tail;
  reg[31:0] head;
  reg[31:0] count;
      reg[31:0] fifomem[31:0]; 
  reg[31:0] data_out;
  #5
      @(posedge wr_clk)
  begin
    if (reset_w == 0) 
  data_out = 32'h0000;
  
else 
  data_out = fifomem[tail];
end
// Update FIFO memory.
#5
      @(posedge wr_clk) 
  begin
    if (reset_w == 1'b1 && write == 1'b1 )
  fifomem[head] = data_in;
// Update the head register.
//
    @(posedge wr_clk) 
    begin
      if (reset_w == 1'b0) 
head = 2'b00;
 
else if (write == 1'b1 && wr_full ==1'b0) begin
// WRITE
head = head + 1;
 
end
end
// Update the tail register.
//
    @(posedge rd_clk) 
    begin
    if (reset_r == 1'b0) 
      begin
tail = 32'b00;
end
else if (read ==1'b1 && rd_empty== 1'b0)
  begin
// READ
tail = tail + 1;
end
end
 
// Update the count regsiter.
 
      @(posedge wr_clk ) 
    begin
      if (reset_w ) 
    begin
      count = 0; end
      else if(count!=32 & write)
begin
count=count +1;
end 
  else 
begin
    count=count;
  end
    end
      //READ
      @(posedge rd_clk)
     begin
      if(reset_r)
 begin
        count=32;
 end 
       else if (count!=0 && read)
begin
         count=count-1;
end
// Concurrent read and write.. no change in count
  else
begin
    count = count;
 end
    end
  
 
 
// *** Update the flags
//
// First, update the empty flag.
//
   @(count) 
    begin
     if (count == 0)
force rd_empty = 1'b1;
else   
force rd_empty = 1'b0;
end
// Update the full flag
//
  @(count) 
    begin
   if (count == 32)
force wr_full = 1'b1;
else
force wr_full = 1'b0;
end 
  end    
     endtask
   initial 
  begin
  queue;
    $display("data_out=%d,wr_full=%d,rd_empty",data_out,wr_full,rd_empty);
  end

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