How to generate a pulse in Verilog-A

[Slavian]

Hello. I've found a verilog-A code for generating a pulse (in the attached txt file).
The problem is, that when I'm trying to run it (using Cadence Virtuoso) I don't see any graph, only the following message is displayed:
"Unable to plot expression <VT("\net5"...(itc.) because it does not evaluate to an object that can be plotted, like a waveform or parametric wave. See the Visualization & Analysis Tool documentation for information about the types of objects that can be plotted in Visualization & Analysis Tool. Only the expressions that evaluate to those objects can be plotted."

Does anyone know what does it mean and how to make it work?
Thanks.

 

[rank0053]

I have a colleague that is having the same issue. Did you ever resolve this issue?
Thanks

 

[erikl]

include it into a schematic netlist and run a transient analysis!

how to make it work?

Did you include it into a schematic netlist and run a transient analysis, plotting the appropriate node?

 

[rank0053]

I'm not sure what you mean. Yes it was put into a schematic. Then a netlist was generated. We can't plot the node. That's why there is a problem and I'm asking for help.

 

[erikl]

Yes it was put into a schematic. Then a netlist was generated.

If you work from schematic, you must put a pulse source symbol (AFAIR it's called vpulse in Virtuoso analogLib) between GND and the input node. You can program the type and form of the pulse if you edit (q) the symbol. The pulse from your above code can easily be programed.

If you decide to use your own Verilog-A code, you'd have to create your own symbol for it. In this case I'd copy the vpulse symbol to a symbol with another name (e.g. my_pulse), edit and change its view to your taste, and make it point to your Verilog-A code file. And then copy your my_pulse/symbol view to a my_pulse/vlog view (AFAIR). But this is library stuff, and I wouldn't necessarily suggest to do that if not absolutely necessary; you'd have to create and include your own library for this, as you're usually not permitted to add stuff into the standard Virtuoso libs.

 

[rank0053]

I don't really care much about how to make the source. I care more about why signals coming out of a verilogA block can't be plotted. Has anyone out there seen this problem, and how did you fix it?

 

[erikl]

I willingly concede that it would be nice to have the possibility to display the behavior of a Verilog-A source without the necessity of a simulation, but I don't know, however, of another appropriate method or tool. May be it exists (I've seen this with other design tools), so I'd suggest to search in more dedicated forums like the **broken link removed** or the Designer's Guide Verilog-AMS forum.

Would be nice if you'd find such a method/tool and you'd report it back. Good luck, and thanks in advance!

 

[dick_freebird]

I recall having to instantiate a trivial resistor to "force the veriloga
currents / voltages to the surface". More of a workaround than a
solution.