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How to generate a clock using a 1Hz clock in Verilog?

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vimedu

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Hi guys

I have a problem: That is :

Using a 1Hz clock, how to generate another clock say 13 Hz? How to model this scenerio in verilog?
 

CLOCK GENERATION

Can be done by a PLL, either analog (e.g. CD4046) or an "all digital" PLL (DPLL respectively ADPLL) logic design.
The latter could be modelled in Verilog.
 

CLOCK GENERATION

Does your code need to be synthesizable?
 
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    vimedu

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Re: CLOCK GENERATION

Yes i want my code to be synthesizable.
 

Re: CLOCK GENERATION

you can use pll . it is best way to generate 13 hz from 1 hz
take a high frequency oscillator of >= 84Hz. you get 13 Hz

search for all digital phase locked loop documents in net... you will get some ideas in implementing that
 

Re: CLOCK GENERATION

Does anyone have start up material/document for frequency generation using PLL?

Thanks in advance
 

Re: CLOCK GENERATION

If you can't afford PLL and your design is not sensitive to duty cycle variations, then you may want to consider a 2-input XOR. Put a delay buffer on one of the inputs and then tie the two inputs together. This gives you clock time two. Chain as many of them together as necessary to get higher multiplications. At the very last stage you can register the output to even out the duty cycle. Also, you may have to manually adjust the buffer delay to 1/2 of your clock period during layout.
Note that this does not give you odd multipliers. For that you need to use counters to count both edges...
 

CLOCK GENERATION

Search all digital PLL in google. U can get the required documents
u have to use two divide by N counters.
have to design divide by N counters. Nothing complicated more than that
 

Re: CLOCK GENERATION

you can get it in google. or try in search engines.

I know the paper which will provide you complete details regarding clock dividers and pll

"clock divider made easy" topic search in google and you will get the link for download
 

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