How to generate 64ns delay from signal without using R/C?

[Death]

i need to generate 64ns of delay from the input signal ...is there any way to achive the same without using R/C ...

 

[Old Nick]

Re: delay logic

https://uk.farnell.com/jsp/Semicond...AS/DS1021S-25+/displayProduct.jsp?sku=1306314

This'll do it. Or something similar, search for delay line.

Maxim IC make quite a few!

 

[Fom]

Re: delay logic

Do you mean on-chip delay or off-chip delay?
If on-chip you can use long channel transistors, but PVT (Process-Voltage-Temperature) deviation can vary this delay 2 times.
In my case I wanted more than 50ns delay. Actually PVT deviation was from 50ns to 100ns.

 

[Death]

Re: delay logic

i need on-chip delay generator by using cmos logic ..like inverters ....im in a position to generate 8ns of delay by using inverters but i need to generate 64ns ....if i use this meathod it will be long chain of inverters and as u mentioned it will not be accurate across corners...this is 65nm technology....

can u tell me how did u impliment it ...a snapshot of the ckt would be of great help.

Added after 1 minutes:

And one more thing is input frequency is variable henceforth we cant use DFF

 

[Fom]

Re: delay logic

can u tell me how did u impliment it ...a snapshot of the ckt would be of great help.

I cannot post snapshot because my computer with design data has no connection to internet.
The implementation is also a chain of inverters with long channel transistors. And it will be always not accurate. My target was a minimal delay more than 50ns. Actually it deviates from 50ns to 100ns.
If you use a standard cell library you can look for a delay cell and use that instead of inverters. But the delay will also deviate like for inverters.

 

[hr_rezaee]

delay logic

Hi
use inverters with large capasitive load.
you can use moscap as load.
This is my idea but I don't know that it is general or not.
regards

 

[jluhzw]

Re: delay logic

You can try by method. The following is the schematic.It is a rising side delay circuit.The delay time can be setted by the resistance and capacitance.
By the way the delay time may also vary with the process.
**broken link removed**

 

[hung_wai_ming@hotmail.com]

delay logic

Current based delay cell, where current is generated from some supply and temperature independent current reference, to minimize delay variation, happens in simple inverter cells