How to generate 10.23MHz from 100Mhz clock!

[42karim]

10.23mhz

hallo guys,

I need to generate exact 10.23MHz clock from 100Mhz input clock, but cannot understand how to do it.Can some body help me in this regard.The device is XC2S200 of Spartan 2 family from Xilinx. I am using verilog as coding language.

Regards,
Karim

 

[rfmw]

10.23 mhz

DDS algorithm?

 

[Iouri]

10.23 mhz clock

use PLL

 

[hcet]

verilog clock divider 100 mhz to 25 mhz

Hi Karim,
I have a similar problem.



Read the following document. It may help you. There are also source examples.

https://www.xilinx.com/bvdocs/appnotes/xapp174.pdf

use PLL

Please, can you explain that!

ep20k

 

[sheik_vb]

oscillator 10.23mhz

Hi,

You can use the DCM CLKFX output.

100 * M / N = 10.23.

If M = 4 and N = 39 then you will get around 10.25.

 

[ahmad_abdulghany]

xilperl

Hi,

You can use the DCM CLKFX output.

100 * M / N = 10.23.

If M = 4 and N = 39 then you will get around 10.25.

Good idea.

P.S. i don't recommend to be DCM dependant in your design

Regards,
Ahmad,

 

[hcet]

vhdl generate 25 mhz clock from 40 mhz

Hi,

You can use the DCM CLKFX output.

I don't think so. XC2S200 has just DLL, not DCM.

ep20k

 

[telga]

dcm fractional divider

Hi 42karim,

Have a look to the perl script available at :

https://fractional-divider.tripod.com/

Telga

 

[wiztronix]

dual modulus divider (pdf)

how to do verilog from a perl script??

regards,
wiztronix

 

[hcet]

why 10.23 mhz

how to do verilog from a perl script??

Look at the fracn09.pl script in fracn09.zip from https://fractional-divider.tripod.com/
Maybe a start :?:

Thanks Telga for this hint

ep20k

 

[42karim]

dds external dac

DDS algorithm?

Well, i have serched for DDS algorithm,.....but came across various ICs that use DDS technology......can some one tell me if i can implement this algo on FPGA!

One thing is for sure.....using DDS we can generate any frequecy approximately to one third of the crystal frequency with accuracy up to 1 Hz in several cases!

Regards,
Karim

 

[telga]

référence at 10.23 mhz

42karim,

Look @ my first post on this topic.
The perl script can generate for U vhdl code who make the requested job.

Example:

perl fracn09.pl -v -f divider 100e6 10.23e6

The dual modulus divider will achieve a 0 Hz error generator.
All characteristics are embedded in the generated file.

If you have not a perl interpreter, let me a message and I publish the generated code.

Telga

 

[IBO]

achieving a 10.23 mhz clock

Harmonic generator

 

[echo47]

frequency divider from 40 mhz to 10.23mhz

This discussion is a few weeks old, but ...

If you are using Xilinx ISE, it includes perl: xilperl.exe.

The fractional divider technique generates jitter that may be undesirable for the application.

The DDS technique can generate a nice low-jitter clock, but it requires an external DAC, low-pass filter, and comparator. You choose the accumulator width to achieve whatever frequency resolution you need, or you can use a modulo or non-binary accumulator to get an exact frequency ratio.

 

[lianghs]

generate 48 mhz clock

If you do not care about the phase and scale, you can use a counter to do it.
If a precise clock must be generated to driving the design, you had better take another oscillator.

 

[global]

perl verilog clock

Hi,

You can use the DCM output.

100 * M / N = 10.23.

If M = 4 and N = 39 then you will get around 10.25.

 

[dll_embed]

verilog + generate 10 mhz clock

If a 1.15M jitter is within your tolerance level, then a simple counter would be able to produce precisely the required clock.

 

[sp3_kapil]

DDS algorithm?