frequency divider from 40 mhz to 10.23mhz
This discussion is a few weeks old, but ...
If you are using Xilinx ISE, it includes perl: xilperl.exe.
The fractional divider technique generates jitter that may be undesirable for the application.
The DDS technique can generate a nice low-jitter clock, but it requires an external DAC, low-pass filter, and comparator. You choose the accumulator width to achieve whatever frequency resolution you need, or you can use a modulo or non-binary accumulator to get an exact frequency ratio.