How to further reduce the leakage current of an IC?

[marshel]

In powerdown mode, some chip have leakage of 1uA, but other just have 10nA current.
How to achieve that?

Thanks.

 

[SkyHigh]

1. Power-gating
2. Clock-gating
3. Subthreshold Operation
4. Multi-Threshold CMOS
5. Increase Threshold

 

[marshel]

Thanks, I have just found a paper about how to decrease leakage current. The paper metioned power gating and multi-threshold cmos.

 

[babbage]

SkyHigh, can you show me the detailed information about this?
Thanks!

 

[SkyHigh]

SkyHigh, can you show me the detailed information about this?

Sure! Search the IEEE Xplore for papers published by Kaushik Roy, Gary Yeap, Chandrakasan, Rabaey, Brodersen, Gwee, Yeo, Nairn, Toumazou, Haigh, Arslan, Chang

You can also search for papers using keywords such as MTCMOS, Variable threshold, subthreshold, power-gating, clock-gating, memory partitioning.

There are books written by Gary Yeap, Kaushik Roy and Chandrakasan. They are perhaps the three more renowned experts in low-power IC design, with very well-written chapters explaining many ways to reduce power consumption including topics on leakage reduction.