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If the DUT was in VHDL, as such the language prevents you from doing this. However, simulators provide a mechanism to access internal variables in VHDL via VHPI/FLI - programming language interfaces. Which simulator do you use? I know MTI has SignalSpy (Spy is more for probing, but I believe they also have some thing to deposit value), NC has NC_MIRROR (NC_DEPOSIT).
Sometime ago I made a generci package (See https://www.noveldv.com/eda/probe.zip) that wraps these simulator specific calls into more generic ones, so that the user's TB code can remain simulator independent. I made this only for probing, but can easilyy extend this to deposit/force if there is enough interest in the community. Please email me @ ajeetha AT noveldv DOT com if you need this.
Forcing internal signals in design is not a good testbench writing practice.
Try to minimize this as much as possible. This limits testbench reusability.
I mean there will be problem if you change design hirarchy or if instead of
rtl you want the same testbench for netlist.