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How to force a signal to certain value from Verilog testbench?

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gold_kiss

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hi,
how do i force a signal to certain value from testbench. this signal is part of DUT and is deep inside the DUT hierarcy.

Thanks,
Gold_kiss
 

AlexWan

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force signal in verilog

Pls use tb.dut_level1_dut_level2.dut_levelx.signal = value.

Good Luck
 

gold_kiss

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writing testbenches in verilog

yea i got this one ...

initial
begin

force tb_top.dut_top.dut_block.dut_signal = 1'b1;

#500 release tb_top.dut_top.dut_block.dut_signal;

end


thanks guys,
Gold_kiss
 

dadu

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writing testbench verilog

you can also use assign deassign for reg
 

foster_cn

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writing testbench in verilog

but what if the DUT was designed in VHDL?
 

aji_vlsi

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writing verilog testbench

If the DUT was in VHDL, as such the language prevents you from doing this. However, simulators provide a mechanism to access internal variables in VHDL via VHPI/FLI - programming language interfaces. Which simulator do you use? I know MTI has SignalSpy (Spy is more for probing, but I believe they also have some thing to deposit value), NC has NC_MIRROR (NC_DEPOSIT).

Sometime ago I made a generci package (See https://www.noveldv.com/eda/probe.zip) that wraps these simulator specific calls into more generic ones, so that the user's TB code can remain simulator independent. I made this only for probing, but can easilyy extend this to deposit/force if there is enough interest in the community. Please email me @ ajeetha AT noveldv DOT com if you need this.

HTH
Ajeetha
https://www.noveldv.com
 

AlexWan

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force release verilog signal

dadu said:
you can also use assign deassign for reg

I am confused for your opinion.
"assign" is for wire type.

We evaluate reg in "initial" in the testbench.

Good Luck
 

aji_vlsi

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how to force a signal in verilog

AlexWan said:
dadu said:
you can also use assign deassign for reg

I am confused for your opinion.
"assign" is for wire type.

We evaluate reg in "initial" in the testbench.

Good Luck

There is also a "procedural assign" in Verilog - less used though.

Ajeetha
https://www.noveldv.com
 

nand_gates

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verilog force signal

Forcing internal signals in design is not a good testbench writing practice.
Try to minimize this as much as possible. This limits testbench reusability.
I mean there will be problem if you change design hirarchy or if instead of
rtl you want the same testbench for netlist.
 

zhangpengyu

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verilog forcing signals

It's better to drive input signals to force interal signals.Driving interal signals directly is not good!
 

gaonkc

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verilog deposit

your can use force ... release to do it
 

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