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how to fix timing violations in SOC encounter

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vlsitechnology

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soc encounter violations

I am doing a project can anyone help me how to fix total DRVs

After doing post route optimization i got total DRVs as ( max fanout, max cap, max transition)= ( 98,38,0) and real DRVs are (0,0,0)

Plz help me its urgent
Bye take care
 

fail1

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timing violations in soc

Normally, we dont care about the fanout violations.

For cap violations,check the drv report & select the pin which has cap violation in the GUI.
Now, look for the instance which is driving thsi high cap pin.
Try to upsize this instance & you should see some cap violation improvement..
 

iwpia50s

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drv soc encounter

If you want to reduce max_cap violations you can set max_tran to a lower value, re-optimize, then set you max_tran back to original value and run drv check again...they should either be gone or greatly reduced.

Added after 52 seconds:

Note, when I say re-optimize, I mean run drv fixing again.
 

vlsitechnology

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pin timing encounter

But these max cap violations are external which means it is there in the i/o pad so how can i upsize that and downsize that
?

Added after 1 minutes:

Hello iwpia but how can i set max trans to a lower value?? bcz in sdc it will be defined right? so we can't change the sdc file am i right?
 

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