How to fix this clock gating check problem?

[jery_cn]

Lastly ,I encount clock check problem.Description as follow :
RTL :
always @(posedge clk0)
clk_gate <= ....


or or(.Y(clk_gate_out),.A(clk0),.B(clk_gate));


always @(posedge clk_gate_out)
.....
.....
DC:
create_clock .... clk0
set_clock_gating_check -setup 0.4 -hold 0.2 [get_cells or]

in order to bypass DC analyse or/B -> clk_gate_out path,I use set_disable_timing -from B -to Y [get_cells or]
But in fact. if i use disable timing,then clock gate check useless. if I remove disable timing ,clock tree use or/B -> clk_gate_out path which
is false. How can resolve this problem?


tks !

 

[shobhit]

It seems that you are generating a signal and this signal is gating the clock via an OR gate, if by design you are sure that this generated signal will be static throughout the functional operation of the design then there is no need to check the clock gating at this OR gate, but if it is not static then you need to check clock gating .

In order to avoid clock gating problem you can instantiate a Clock gate cell instead of OR gate / another solution could be that you can implement the same logic using a 2 input mux.

thanks,
Shobhit

 

[jery_cn]

Thanks for your information! what is the "using a 2 input mux",Does this can resolve the dynamic gating signal?

 

[shobhit]

Say there are two inputs to an OR gate. One is 'clk' and another signal 'A' so when signal 'A' is 1 then clock is gated and output is 1 otherwise it simply passes therefore
If we take a 2 input MUX with inputs D0 & D1 and select S. If we connect D0<----->clk and D1<----> 1'b1 and S<---> signal 'A' we can achieve the desired result. As when S will be 1 output of mux will be pulled to 1 and clock would be gated and if S is 0 the clock signal would simply be passed. In a similar way gating by an AND gate can also be implemented by mux. MUX implementation would remove clock gating problems.

 

[jery_cn]

How can this "mux" avoid glitch on mux's output which is a clock?