How to fix setup and hold violations?

[vsrpkumar]

Hi
How will fix set up and hold violations..Give me the exact answer.Thanking you
kumar.Give me saw material

 

[nmurthy]

Re: query

hi i know very little abt this one

to minimise set up time increase the input frequency
to minimise hold time use buffer insertions

please correct if i am wrong

 

[shankarmit]

Re: query

To fix set up violation,

one thing is optimizing the combinational logic in the critical path.. if its not possible using pipelining concept thats...divide the combinational logic using a register in critcal path.if that is also not possible, then
add buffer in the clock data path to 2nd register to meet the setup time..

To fix hold violation..

Insert some buffer in the critical path.. but ensure that that does not affect setup time as combinational logic propagation delay get increased...

Regards
Shankar