how to find stuck-at fault for flops

[jaydip]

Stuck-at fault for flops

Hello,

ATPG can find stuck-at faults of combinatorial logic of the design. But, how to find faults within a flop ??? how can we find stuck-at faults, if occured, for flops. because while ATPG generates patterns it takes flops as granted (means, it assumes that flop does not have any stuck-at fault).

 

[FvM]

Stuck-at fault for flops

Can you give a simple example of what you regard as "fault within a flop"?

 

[jaydip]

Stuck-at fault for flops

flop is nothing but a collection of gates or say transistors, right? so, now the way stuck-at 0/1 faults occur for combinatorial logic, it can happen for flops as well, right? and that is what i m referring to as a "fault within a flop" ..

i hope it is understandable ...

 

[RBB]

Stuck-at fault for flops

Usually ATPG assumes only faults at pins of cells. Do you want to run your fault coverage with faults internal nodes within the flop? Why would you want to do this?
I'm guessing you would need to model the flops as it is structually built (i.e. not using UDPs) and then add the internal flop faults.

 

[owen_li]

Re: Stuck-at fault for flops

Hi.

Actually, when we apply the test patterns, we will usually shift the patterns to check if the flops are well. In this action, there will be no capture step, and just the shift in and shift out to test the flops.
Hope this will help you!