How to find pins suitable for differential clock (Spartan7 FPGA)

[FlyingDutch]

Hello,

in my last design in FPGA I encountered difficulties with differential clock pins. My FPGA board is:

https://pl.aliexpress.com/item/32959887279.html?spm=a2g17.12010612.8148356.4.1a4954bdnHb81i

with Spartan7 IC - exactly XC7S15-FTGB196

In Vivado project I made block design of Microblaze MCU. This block has input of differential clock (100MHz) as it's input port. On My FPGA board I have single clock of frequency 50 MHz..
In order to provide such clock to MCU desing I used clok wizard IP where i generated 100 Mhz single clock. Then I input this clock to OBUFDS primitive and from it's outputs go out two pins of differential clock (n and p).

My question is how to find for this Spartan7 chip and map in constraint file suitable pins for such clock.

I am showing a part of VHDL code with clock wizard and OBUFDS buffer:

PLL: clk_wiz_0 port map (clk50MHz,reset_rtl_0, clk100MHz);

 --Output buffer for diff clock (out)
 OBUFDS_buffer : OBUFDS
    generic map(
       IOSTANDARD=>"DEFAULT",   --SpecifytheoutputI/Ostandard
       SLEW=>"SLOW")            --Specifytheoutputslewrate
    port map(
      O => Odiff_clock_rtl_0_clk_p,      --Diff_poutput(connectdirectlytotop-levelport)
      OB => Odiff_clock_rtl_0_clk_n,     --Diff_noutput(connectdirectlytotop-levelport)
      I => clk100MHz                     --Bufferinput
    );

i am also not sure if IOSTANDARD=>"DEFAULT" is OK, or should I explicite give one of differential standars (for example DIFF_HSTL_II_18).

Could I ask for help with this question?

Best Regards

 

[KlausST]

Hi,

I´m no expert here...

differential clock...
* inputs make sense since the clock is spread over the whole chip
* but for output you may use any "differential output" (no need for dedicated "clock")

you should read
--> UG475 for general pinout informations
--> DS189 for voltage and timing specifications
--> UG471 forthe SelectIO resources
--> https://www.xilinx.com/support/packagefiles/s7packages/xc7s15ftgb196pkg.txt for detailed pin names
I guess especially the "IO_LxxP.." and "IO_LxxN..." pins.

Klaus

 

[FlyingDutch]

On my board pins A12 and A13 seems to be suitable

Thanks very much @KlausST

 

[FvM]

In Vivado project I made block design of Microblaze MCU. This block has input of differential clock (100MHz) as it's input port.

Why? What if you assign a single ended clock input instead?

 

[ads-ee]

You should have the option to build your BD with a single ended clock for the Microblaze. I've been able to do this in the past as almost all the embedded processor focused development boards only have a single ended clock source e.g. 100 MHz oscilator on the board.

 

[bansalr]

Use pin assignment application in vivado ...it will help you with all PIN assignment constraints and check legality ....

 

[FlyingDutch]

Hello,

Vivado itself added differential clock in clocking wizard for uBlaze. See screenshot from uBlaze block design:

Ok I changedthis port into single clock input on BD. Thanks all for hint

Best Regards

 

[std_match]

It is a really bad idea to include clock buffers in block designs, since it makes it impossible to share the clock between blocks.
You can route the clock output to an output from the block design to make it available for other blocks, but that doesn't help if you have two block designs where both include a clock buffer. Only single-ended clocks to block designs, and no clock buffers in there!