Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to find delay caused by longer Poly layer and how to reduce this delay

circuitking

Full Member level 4
Joined
Jan 8, 2018
Messages
222
Helped
1
Reputation
2
Reaction score
1
Trophy points
18
Activity points
1,950
Dear all, In my layout I have many transistors and their gates are connected directly with poly layer. I want to find the delay caused by this long Poly line, could you tell how can I find it?. If this is too much, what methods do I have to reduce it. I heard that I should keep poly to M1 vias, could you tell more about it. Thanks
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
6,852
Helped
2,011
Reputation
4,026
Reaction score
1,846
Trophy points
1,393
Location
USA
Activity points
54,903
If your tools*PDK support RC extraction then maybe
this gets done for you, and you just need to run a
simulation based on the analog_extracted (or
whatever) view.

Or, you go and measure poly squares and determine
poly doping -> poly sheet resistivity (poly may see
various dopings depending on what it's routed
over and "tagged" as - N+, P+, silicide, no silicide).
Just put that in each leg as a properly connected,
properly parameterized presistor and let the FETs'
gate load "be what it is" (for short haul routes over
field, net capacitance added should be trivial). If
you feel like the net is significant you can always
calculate fringing + plate line capacitance and
add as a pcapacitor..
 

Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top