for checkmate......................
this thing comes when two or three nmos are stacked and you want to calculate what is the value between the nodes like in case 3-input nand gate in which 3 nmos would be stacked.... to find the exact output low voltage you need to know how you will analyse these type of ciurcuits................
Added after 3 minutes:
for deepuj............
how did u say these statements...............
about your first statement.... if you apply vin less that vth then both nmos would be in off condition then how can you say low pulse will short vcc to ground..........
for checkmate......................
this thing comes when two or three nmos are stacked and you want to calculate what is the value between the nodes like in case 3-input nand gate in which 3 nmos would be stacked.... to find the exact output low voltage you need to know how you will analyse these type of ciurcuits................
ok... i know there will be 3-pmos if i use cmos technology.... but what will happen if i use only one saturated depletion mode transistor in place of three pmos... it will also work as nand gate but the problem is that there will be some value at output node(output low voltage) if i apply vdd to all inputs of nmos this happens becuase of stacked nmos...