I am doing a project whr i have implemented 2D DCT in VHDL and also tested with input matrix and working correctly.The inputs are fed 8 bit at a time for an 8X8 block input. so after 64 clk pulses the matrix is formed inside registers.
I am using Aldec active HDL for hdl simulink interface and i know how to do that also.
My question is when i need to fetch a 2D image how can i give the input since my block only accepts 8 bit at a time..but simulink will try to put the whole data into it and dimensions become wrong in interface..
can u brief on that pls.. means i must also write a testbench of that file? if u want more details i can paste my vhdl code here for ur further reference.
I have done it so that simulink passes me an entire 2D array (annoyingly, the co-simulation block only supports up to 2 dimension) and then there is a behavioural process in my wrapper pulling each pixel out. This is acompanied by a "ready" signal with the image, so the wrapper knows when to write data in. When the wrapper has collected th data it sends it back to simulink via the same method.
This isnt going to work if you expect other pipeline elements to do a job inside simulink. If your entire pipeline sits in co-simulation, then you should be ok.
an example of a behavioural input process:
Code:
process
begin
wait until rising_edge(image_rdy);
wait until rising_edge(clk) --synchronise with the clock
for i in image'range loop
input <= image(i);
wait until rising_edge(clk)
end loop;
end process;
thanks for the reply man... i somewhat understand your concept. So it means that in my wrapper i need to initialize as 64 bit input and from that i need to take 8 bit at a time to my module
VHDL Wrapper--> DCT unit ??
but 2d image means [8X8] block. So how do i send this to my wrapper? since it'll be organized as rows and columns.. for this do i need to put any simulink block? u've any tutorial or link for that....