how to extract design hierachy in irun?

[skyworld_cy]

Hi,
I have a design with Verilog, simulated with irun. Is there a way to extract the hierarchy of the design? I would like to extract all ports of each level and probe them. thanks.


regards
skyworld

 

[tariq786]

you have to use +access+rwc on the command line and dump using VCD or .shm format.

If you want to just get the hierarchy, i would recommend you look at

https://www.veripool.org/wiki/verilog-perl

On this page, look at Verilog::Netlist. It would be very useful if you look at its documentation and run some examples

https://www.veripool.org/projects/verilog-perl/wiki/Manual-verilog-perl

 

[imbichie]

You can use the " . " (dot) operator to call the Ports and Internal signals.
For example if your top Tb is TB_TOP and your top module instance is TOP, and if there are modules instantiated inside the TOP as A1, A2, etc.
And if A2 have port called clk and if you want to access that port you can do like this :
TB_TOP.TOP.A2.clk
which will bring the clk port of A2