oho
Newbie level 4
I'm using Libero SoC 11.8.2 SP3 for a design on an ASICPro3 FPGA, and when opening the timing analysis I can find the different critical paths (register to register), but it only gives me the source and sink pins, and I have to manually expand each one to see the full path. Is there a way or a script that can export all the full paths at once instead of doing each one manually, because my design can have over 1000 paths that I need to expand, and it is very tedious to do them by hand.
This is the paths view:
And this is the expanded full path view:
Thanks!
This is the paths view:
And this is the expanded full path view:
Thanks!