I believe engineer need to check waveform to make sure the UVM work correctly or not.
But anyway, are you sure that we can not create waveform in UVM run ?
Waveform viewing of a design in independent of the testbench used to simulate the design. If you want to view the class-based UVM data, you need to look at the User Manual sections on SystemVerilog Class Debugging and UVM-aware debugging. You might need Questa to do this.
I could make wlf out adding the "add wave" after vsim. The reason is that Modelsim can not save a wlf file if you don't add a signal to waveform pane. There is another way using wlfdumpvars(), but have not tried. Thanks guys.
I can see vsim.wlf outputted in normal simulation. I wonder there is a command needed in UVM.
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I believe engineer need to check waveform to make sure the UVM work correctly or not.
But anyway, are you sure that we can not create waveform in UVM run ?