How to explain Verilog compilation error and warning

[Fom]

spectre verilog warnings

Cadence AMS simulation
After compilation there are some error and warning messages with some code at the end of these messages. Like:

[Verilog-ICMP]
[Verilog-TFNPC]
[Verilog-PNFMD]

Where to find meaning of these codes. As I remember there shoud be a special comand running in terminal window. If to run this command with code it will return the explanation of that. It seems before I used this command, but now I don't remember how to run it.
Can anybody help?

 

[sree205]

verilog compilation

Hi, if you have a sourcelink ID, it'll be easy to search in cadence site itself. I'm posting the description for Verilog-ICMP, let me know if this is what you are looking for.

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spectreVerilog creates incorrect netlist for single bit bus

Error Message:
Error! Illegal connection to module port (IB) [Verilog-ICMP]
"ihnl/cds1/netlist", 27: .IB(net5)

Problem statement:
You are running spectreVerilog simulation with single bit bus pin in your design.
E.g. Take a simple inverter with input pin as ib<4> and output as say out1.
When you netlist your top level schematic with this inverter instance, you will see
the following netlist, which parser complains.

module MYinv ( out1, ib[4] );
output out1;


input [4:4] ib;
supply0 gnd_;

...

Simulation gives following error

Error! Illegal connection to module port (IB) [Verilog-ICMP]
"ihnl/cds1/netlist", 27: .IB(net5)
It used to work in IC5141USR1 release.

Solution:
PCR 857139 has been filed for this issue. This is fixed in the IC 5.10.41.500.3.30
& 5.12.41.500.3.30 releases. You may download the latest ISR from https://downloads.cadence.com.

During explicit netlisting in case of single bit bus the single bit was not dropped even
if drop port range is enabled. It has been fixed. Now in latest version you will get
following netlist:

module MYinv ( out1, ib );
output out1;


input [4:4] ib;
supply0 gnd_;

...

The simulation will run without errors.