How to estimate the layout area of the power transistor?

[shaq]

Dear all,

Suppose my size of the power transistor is w=900um l=0.7um
If I use the "waffle" style of layout method, how do I estimate the layout area of the power transistor?

(the spacing in a contact to poly gate is 0.4um, the min. gate poly is 0.5um)

 

[jttzeng]

Do you plan to draw the power mos with how many fingers (m= ?)

 

[shaq]

Do you plan to draw the power mos with how many fingers (m= ?)

Dear jttzeng,

Suppose that I assume the W=9um L=0.7um M=100 (sorry, this is my first time to draw a power mosfet in a layout in my life, so I don't know how to determine the unit size of the transistor.)

Is it reasonable?

 

[shaq]

No body knows?

 

[mince]

Just do some math. I don't know how big your contacts are, but suppose they're .4x.4. If you make the layout 10 rows of 10 fingers each, plus maybe a dummy on each side then you'll have 12 * .7 = 8.4 um in total gate length. For the area between gates, you'll have .4 on each side of the contact plus .4 for the contact = 1.2 um. You'll have 12+1 of these so 13*1.2 = 15.6 um. Total width will then be 15.6+8.4 um = 24 um wide. Height will be 9 u x 10 rows = 90 um. Probably want to add about 10-20% to this number for spacing between rows, so make it 105 um. Total area then will be 105 x 24. That's how you can calculate it....optimize it to however you want it to be, using the correct value for gate to contact distance plus contact width.