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You can calculate it. But you will not be able to calculate the exact Area. Somehow you can predict 75% of the area & 25% may vary as the placement of the transistor might vary due to Physical rules.
To estimate the blocks' area, the best way is to find the area of similar blocks done before. If you have no reference, it will be boring.
With the guideline of the area of blocks and the sketch of bonding, u can do floorplan, place Blocks/Power Device/Pad/ESD/Seal ring/Routing area/scribe line on the chip.
You can use the Layout XL tool for area estimation.
In your schematic window, you can go to Tools->Design Synthesis->Layout XL. It will open a layout editor window. From there, you can go to Design->Generate from source. In this form, on the bottom left, you'll have the area utilization option where you can fill the percentage of the total area. This depends on the routing line widths, and matching constraints.
The general rule is that for low power analog circuits, you can use an area of around 65%~75%. for high power circuits, it can go down to 55-60%.
For custom digital circuits, it can be 80-85%.
Again, these will only give you quick rough estimates.
Nothing like doing a detailed floor plan.
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