Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to estimate constraint value for DC after test from vcs?

Status
Not open for further replies.

siva_7517

Full Member level 2
Joined
Jan 16, 2006
Messages
138
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,401
constraint setting

hi,

How do we set estimate constraint value for dc after functionality test from vcs :

set_clock_latency
set_clock_uncertainty
set_clock_transition
set_load
set_output_delay
set_input_delay
set_input_transition
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top