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How to estimate chip power consume?

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In SOC stage, Software and hardware co-work is essential, so power consume estimate per-design raised. Estimate chip MIPS/MOPS requirement and power consume in working mode or IDLE mode is a very important work in system architecture design. How to estimate full chip or system power consume before P&R?
 

PrimePower could do power estimation on RTL, netlist before P&R and netlist back annotated with parameter after P&R.
 

PP (PrimePower) + System Function Pattern run on netlist before P&R
 

Who has experience using PowerTheater from Sequence Design?
 

Powermill is good i heard..how abt FLOPSI -=- framework for low power system intergration.(synopsys)

COMPASS design automation is there . this has its own framework. this belong to EPIC technologies.

You have HSPICE with templates which you can use for power analysis.

XPOWER by Xilinx helps for power analysis of asynch ckts.

Powertheater i think is used for RTL and circuit level power analysis.
PowerTheater - Low Power Design & Power Analysis For Nanometer System-on-Chip Design.This tools helps in extracting the maximum efficiency out of our design.
It provides accurate gate level power analysis and simulation results.

primepower is also there,synopsys tools is also used for optimization

most scripts are written usin perl/tcl scriptin which is the last phase in power analysis.

I think MAGMA design automation is a good tools for power analysis

h**p://www.magma-da.com/articles/Magma_Low_Power_White_Paper.pdf

This is the only tools (I THINK - Plz correct me if am wrong) which supports RTL-GDSII format for power analysis and optimization.

take a look at this too

h**p://www.ascinc.com/products/low_power/

hopw this might help you,

with regards,
 

wicho said:
Who has experience using PowerTheater from Sequence Design?

I work with PowerTheater , how could I help you ?
max
 

onailimissam,
Can you please tell us how much the PowerTheater's result are accurate? How do you compare it with Hspice or NanoSim (accuracy, analysis time)?
 

omid219 said:
onailimissam,
Can you please tell us how much the PowerTheater's result are accurate? How do you compare it with Hspice or NanoSim (accuracy, analysis time)?

I can give you some numbers because I had to estimate powertheater accuracy on some vhdl blocks.

First of all i did an RTL analysis using vhdl files and technology info in powertheater, then I used a verilog netlist and i compared the two flow with powermill results.

Here below the results:

10 Mhz clock
1.5 volt
powertheater=P.T.
P.T.(RTL) P.T.(gate level) powermill
control block (state machine) 39.8 uW 45 uW 42.9 UW
reset manger 16.6 uW 18.6 uW 17.25 uW
uart 140 uW 42.8 uW 50 uW
timer 113 uW 29.1 uW 32 uW

some remarks:
## the mismatvh between RTL and powermill results are because the gate level is with clock gating: not al all included into vhdl descriptions,
##powertheater estimates capacitance and wireload model in rtl flow, it is possible to overwrite this value with a more accurate one getting better results also with rtl flow estimation,
##transition times are also important, again powertheater estimates this value equal for all the gates in rtl flow, again is possible to change this value with more acurate one.

RTL analysis is very fast compared to powermill of course, also netlist analysis is faster then powermill and accuracy is quite close to powermill values, and this is even surprising if you think that you need only to provide .vcd file (switching activity) , netlist, technology file (.lib) and push the botton !
Powermill is much more trichy to use and longer....

I hope this will help you,
max
 

Thanks onailimissam for the info.
Do you have any idea about PT's price? Is it cheaper than power mill?
 

I have no idea at all about prices..sorry, and i do not know how to get this info, on the sequence web site there is no indication about that, like usual for all of these eda products.
I am in a big company and nobody cares about prices for tool , hoh well ... nobody between designers :D
 

I think Magma Blastpower and BlastRail tools have good power analysis capabilities as I have worked on them. They can calculate power throughout the flow right from gate level to final silicon. If you have the VCD information of your netlist andthe spice files, You can get a near accurate estimate using Magma tools.
 

I have never used these tools, but it seems you can not do rtl estimation isn´t it ?
For power architecture optimization is mandatory do power analysis
early into design flow, as long as you go further with design flow the power optimization you can do decrease of importance, that´s why i like powertheater , because you can get faster and meaningful results at rtl level, if you know the behaviour of the tool.
 

we follow PKS low power flow, and employ voltage storm to analyze IR drop and EM.
 

PrimePower can do power estimation on RTL, netlist before P&R and netlist back annotated with parameter after P&R.
 

does someone else use powertheater by sequence ?
I need help.
Many thanks,
max
 

Who can provide some papers or user guide of the powerthetre flow?
 

onailimissam said:
does someone else use powertheater by sequence ?
I need help.
Many thanks,
max

I use power theater how can i help u
 

First , You must give the frequency of the per IP running. secondly, you may run the primepower or powertheater to chech the overturn
 

how do we calculate power using PKS?????? or in SOC Encounter..


regards,
Prasad
 

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