How to ensure the duty equals 50% in PLL design?

[ala]

PLL

I am designing the PLL、
How to ensure the duty to equal 50%?

 

[flatulent]

Re: PLL

Assuming that you mean the AC waveform output, the standard way to do this is to have the basic VCO at twice the desired frequency and use a divide by two logic circuit. One example is a D flip flop with the Qnot output connected to the D input. Then clock it with your 2x frequency VCO.

 

[IanP]

Re: PLL

Include into your design :2 (division by 2) circuit and this will ensure that output wave has exactly 50% duty cycle.
Division by 2 circuit can be simple D-FlipFlop where you connect negative output to D-input or JK-FlipFlop with bothe J and K inputs connected to Ligic H.

I hope we are not doing your homeworks here....

 

[simonkuo]

Re: PLL

Be careful to design the differential to single end circuit ( input comes from VCO output). If the VCO's gain too large, the jitter maybe large.

 

[piao]

PLL

you may need a D-flip flop, however, you should pay more attention to the structure, since it works at high speed, so you may need a other structure to implement such a frequency device.

you can refer to the prescalar circuit in PLL.

 

[EleApollo]

PLL

first of all, u lock your frequence to a higher such as 5~10times, and second you may divide it into the equal duty.

 

[devrimaksin]

PLL

You can use digital counter structure

 

[itaifrenkel]

Re: PLL

which simulators are you using for PLL design ?

 

[eesoko]

Re: PLL

One of the best thing I found for PLL was spectreVerilog simulator included in cadence IC environment. But this is true only if you have complex PLL with large digital core. In such case you can replace analog components (VCO, PFD, Charge pump ....) with veriloga model, and use verilog model for digital cell. This will allow you to evaluate structure in minutes instead of days.

Generaly behavioural modeling of the components that are not under test will cut down significantly your simulation time.

For the full transistor level simulation you can use hsim, it has decent accuracy but is VERY fast (about 4-5 times faster then spectre simulator for PLL case, they claim it is 40 X faster in digital circuit simulations). There is also ultasim and some simulator from synopsis, but I never used either of those.

 

[gargoyle]

Re: PLL

use dff
or duty cycle corrector

 

[qy79]

PLL

duty cycle corrector inside PLL loop or outside ?

 

[visualart]

PLL

The way to do this is to have the higher frequence VCO (over 4 times generally) and use a divider. you will get the exact 1/2 duty