How to eliminate ripples in VCO control voltages

[AdvaRes]

Hi guys,

When the PLL locks I zoom in the signal that controls the VCO. The signals has periodic ripples that occurs at the speed of the PFD/CP. The controle Voltage range is between 0 and VDD. The ripple represent 3.6% of VDD.

Is that big or normal ? Are these ripples the responsible of the reference spurs in PSD plot of the PLLs output signal ?
How to eliminate them without changing the BW and phase margine of the PLL ?

Thanks in advance for your participation.

 

[keith1200rs]

Be careful probing the control voltage - the scope probes can load it and make it worse depending on the type of phase comparator and make it appear worse than it really is. See if the spurs are worse when you probe the control voltage.

Keith.

 

[dick_freebird]

Ripple on the tuning line goes directly to jitter /phase noise.
You would like to filter this as hard as you can, without
violating any frequency-slewing or loop stability requirements.
An up/down PLL often has filtering in the external op amp; a
"charge pump" PLL could just have a capacitor, which you
might append anoher RC network to.

Now, at lock, your charge pump ought to be largely silent.
Unless you have some bleed current removing charge
and requiring the pump to restore it. This is something
you might look into - why is the Vtune line moving up and
down when it should be at rest? Anything that minimizes CP
activity will reduce phase noise.

Also it might not be too far-out, to see 3% worth of ground
bounce in any old branch of a digital circuit. Your reference
point for measurement should be the VCO ref ground.
Check other ground-points, like the PLL's, for how tight
they are to the destination. Return key filter grounds
separately to the VCO ground-point, etc.

 

[Design engineer]

All,

I have an issue with my PLL locking ..

The ripple in my VCO control voltage is non uniform ..so its kind of fluctuating up and down ..B'caz of that my VCO (LC -866MHz .. 1.1547n sec) o/p frequecy is also fluctuating ..i.e. the adjacent cycles of my VCO o/p do not have same clock period ..it slightly varies by 30-50ps in a regular pattern..

So..the Frq divided i/p and my reference are not in phase continuously ... the frequncy divided o/p also follows a kind of regular pattern ( increase -> decrese -> increase) .

I thought that ..the reason could be because of my CP charging &dis cahrging resistance mismatch .. Also, i tried 2nd order loop filetr ..still it didn't help me.

Now, i am totally clueless as to what to do .. appreciate your inputs in this issue.

Icp =45ua , Kvco = 258.94MHz/V , R=300K , Cp = 10.613pF, Cz = 662.914f F

Thanks,