How to eliminate jitter using verilog

[keerthna]

How do i eliminate jitter in a signal using a piece of verilog code? Does verilog uses some key words for the same? I came across this

(SYSTEM_JITTER="VALUE" in ps*);

how do i use this in my module? or is there some other way to do it?

 

[TrickyDicky]

Jitter is a property of an analogue signal.
Verilog deals with digital logic.

Hence nothing you do in your verilog will affect the jitter.

 

[code_slave]

Jitter is a property of an analogue signal.

And of digital signals, in fact everything in the universe suffers from jitter.

 

[TrickyDicky]

Well yes.
But in the digital domain, jitter would only occur during a clock domain crossing.

 

[rberek]

Jitter is clock edge uncertainty and can occur anywhere in the digital domain. If the source of the jitter is the oscillator or any other part of your clock tree, as it often is, then every flop will be affected by jitter. I work on cellular radio digital ASICs and we have no clock crossings in them and jitter is still a concern.

One thing I think we can agree on , though, is that no Verilog construct will magically fix it!

r.b.

 

[pbernardi]

And of digital signals, in fact everything in the universe suffers from jitter.

In fact, quantum theory show us that the universe is digital, not analog!

OT: You can, however, use the constraint cited (SYSTEM_JITTER="VALUE" in ps*); to tell your system what jitter it should expect, and the synthesis will take this value into account when routing your FPGA. But it does not have anything to do with Verilog, you have to insert this line in your constraint file (.ucf)

 

[code_slave]

In fact, quantum theory show us that the universe is digital, not analog!

No … sorry,

'Schrödinger's Cat ' shows us there are at least THREE states.
Dead, Alive …. and something else.

I should not have used such an analogy

OT:
The POINT I was trying to make was that Jitter is something that MUST be dealt with in the design.
It is not just written off with some sort of 'magic' HDL incantation, even within the FPGA there is going to be jitter, which is a FUNCTION of state switching.
Magically setting (SYSTEM_JITTER="VALUE" in ps*); , is not going to make the transistors turn on or off any quicker, Nor is it going to 'magically' control the temperature and voltage of the logic. ( both of which can externally affect jitter).

 

[keerthna]

So if there is no way to eliminate jitter, can I do something to prevent the false triggering of a signal? For example, if I use a counter to increment at every posedge of the signal and it shouldn't increment when the signal suffered from a glitch and is high. That is when there is a false triggering of the signal due to some reason, counter doesnt increment. can i do something like this using verilog?

 

[axcdd]

So if there is no way to eliminate jitter, can I do something to prevent the false triggering of a signal? For example, if I use a counter to increment at every posedge of the signal and it shouldn't increment when the signal suffered from a glitch and is high. That is when there is a false triggering of the signal due to some reason, counter doesnt increment. can i do something like this using verilog?

HI,

First of all Jitter in pure internal digital systems in normal condition (not on some space shuttle, high radiation enviroment) is not a problem at all. Typically clock jitter is few ps compared to setup time equall to few ns, will not cause any errors unless FPGA is run at max range MHz. As mentioned earlier you can inform synthesis tools about clock jitter in *.sdc file to take it to calculation in place&route stage.

As for glitches i'll quote altera design recommended practise:

I"n a synchronous design, glitches on data inputs of registers are normal
events that have no consequences"

 

[TrickyDicky]

So if there is no way to eliminate jitter, can I do something to prevent the false triggering of a signal? For example, if I use a counter to increment at every posedge of the signal and it shouldn't increment when the signal suffered from a glitch and is high. That is when there is a false triggering of the signal due to some reason, counter doesnt increment. can i do something like this using verilog?

If you're using a signal as a clock that may have glitches - the problem here is poor design decisions.
You should always use a good clock source - not some random data signal or internally generated signal as a clock.
Otherwise you may get erroneous counts from the glitches.

Moral of the story - use a good quality system clock for EVERYTHING and generate clock enables instead of using rubbish clock sources.

 

[keerthna]

I am not trying to find if there are any glitches in a clock signal. what i meant was if a signal is generated in some way and if that signal has glitches then is there any way to find out these glitches?

 

[axcdd]

99,99....9% signals that goes thought 2 stage++combinatorial logic has glitches.....
Yes u can find them out if you connect few GS/s scope to internal signals - which is impossible....

 

[keerthna]

So that means there is practically no way to find out if my signal is clean or is suffering from glitches?

 

[axcdd]

You dont have access to internal signals in FPGA, so you have no information about glitches, so its pointless, unless u want to measure FPGA input or output signal, in which case you can use oscilloscope with proper trigger

 

[TrickyDicky]

The best way to avoid glitches is good design practice. If you have used a logic signal as a clock - you have poor design practice. Tracking down glitches is going to be no fun, as they will be dependent on PVT (process, voltage, temperature - process = logic delay which can vary from one compile to another).

So - I highly recommened, if you have used a data signal or internally generated signal as a clock, you re-design the system