Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to eliminate hard switching effects?

Status
Not open for further replies.

seyyah

Advanced Member level 2
Joined
Oct 7, 2001
Messages
646
Helped
8
Reputation
16
Reaction score
8
Trophy points
1,298
Activity points
6,233
hard switching snubber -resonant -soft

How can we eliminate dips or peaks which occur at rising or falling edges of the switching pulses?
 

The question is too common. There are a lots and lots of different kinds of switching pulses.

Varuzhan
 

Without going into details, you can try to use a snubber circuit.
Have a look in here:
**broken link removed**
Regards,
IanP
 

Switchings are pwm switchings up to 20KHz. Actually i use a snubber. May be it needs tuning. I need some info to calculate parameters, can you offer something? Also someone proposed me to connect an rc filter to the gate , but i couldn't understand the use of this. Does this method make any sense to you?
 

Connecting a filter at the gate will slow down the MOSFETs. With slower rise/fall times the induced voltages (in parasitic inductances) will be lower.

The down side is that you will increase switching losses in the transistors. Generally, only a resistor in series with the MOSFET gate is sufficient. I would not add the capacitor.
 

A zener diode may suffice may be, what do you think?
 

you can use RC snubber circuit to have a try.

seyyah said:
How can we eliminate dips or peaks which occur at rising or falling edges of the switching pulses?
 

Maybe this is a stupid suggestion, depending on your experience level, but have you checked your measuring method? Per example, measuring with a scope with long ground leads will also result in perceived ringing on edges?
 

If you mean the peak/dip at rising/falling edge of 'switching signal' (PWM signal to gate), then you should add a resistor in series to the gate of the mosfet. If I'm not wrong, larger resistance value will increase the rising time, and therefore reduce the peak magnitude. However, switching loss will increase. So, need to set a balance.
 

R should eliminate but didn't help so much. I can't increase the resistor very much. Snubber may help, thanks
 

Best snubber circuit is RCD snubber with polyster type cap which reduces almost 60 to 80% spikes
 

first, you must to ensure that your pulse gate of switcher can truly on and off. The second, Your PS must be in continuous conduction mode. Circuit of snubber maybe complex and difficult, if not work in big power maybe u can select device over your design ( current and voltage capability ).
 

I have the same problem, but my device is in integrated circuit. and the inductance is the bonding wire. The breakdown voltage is very little. I can't decrease the rise time. And I can't connect anything with parallel to the bonding wire.
Any idea?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top