how to dump vars in verilog file?

[arsenal]

i wanna dump the signals in verilog simulation to a vector file that can be used in hsim simulation(by .vec <vector file>).
i have tried $dumpvars,but the output pattern cannot be recognized by hsim.

can anybody give me some help?
thx a lot

 

[xuanzhu]

That is to say, your output file format is not fit for HSIM request, I recommend you use perl to do the format conversion. After all, they are both pure text file

 

[nanako]

if i'm not wrong, $dumpvars is dumping for VCD format.

 

[nand_gates]

/* here is an example...
say following are the signal i wish to put in .vec file
input clk pd_out[1:0] phdir phwt_0 phwt_14
output phsel_up phsel_dn phwt_up phwt_dn toggle_dir

*/

module vec_gen();
   integer file_ptr;
   initial begin
      file_ptr = $fopen("sim.vec");
      $fdisplay(file_ptr, "signal clk pd_out[1:0] phdir phwt_0 phwt_14");
      $fdisplay(file_ptr, "+ phsel_up phsel_dn phwt_up phwt_dn toggle_dir");
      $fdisplay(file_ptr, "period 10");
      $fdisplay(file_ptr, "radix 111111 11111");
      $fdisplay(file_ptr, "io    iiiiii ooooo");
      $fmonitor(file_ptr, "\t%b%b%b%b%b %b%b%b%b%b",clk, pd_out[1:0], phdir, phwt_0, phwt_14, 
                phsel_up phsel_dn phwt_up phwt_dn toggle_dir);
   end
endmodule // vec_gen

 

[arsenal]

hi nand_gates,
thank you very much