Suppose a signal is being transferred from high frequency clock domain to low frequency clock domain. How will u do synchronization in tyhis situation?
If you know the frequency or the ratio of fast to slow clock, u can add that many delay stages while the signal is transferred from fast clock, so that slow clock can capture the signal transferred from fast clock domain correctly or u can use handshake mechanism for the transfer from fast to slow clock domain.
I noticed many of your questions on the forum and practically ALL could be answered much more clearly and correctly by the above book.
it is well written and actually an interesting read.
I noticed many of your questions on the forum and practically ALL could be answered much more clearly and correctly by the above book.
it is well written and actually an interesting read.
Harris's books are the best Especially the third edition of VLSI Circuit design. I'm also looking for his book: Skew-Tolerant Circuit Design.
Please if you happen to have them please share it.