Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to do postsimulation with hspice[help]

Status
Not open for further replies.

sophiefans

Member level 3
Joined
Jun 12, 2006
Messages
59
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,748
I am a student. I've never done postsimualtion before. Could someone tell me the detail? Reference with example will be better. And the layout has passed DRC&LVS.

Thanks in advance
sincerely
sophiefans
 

Hi,

do you mean a post-layout simulation? So do you already carried out a parasitic extraction and want to verify functionality after layout?
Please specify the tools you are using for layout, lvs and parasitic extraction. If you are using cadence dfII and assura for parasitic extraction, you get an so called extracted view after parasitic extraction. You can use this view to do the post-layout simulation.
In the attached document these steps are described (in german, but the images carry the important information).

kind regards,
hqqh
 

    sophiefans

    Points: 2
    Helpful Answer Positive Rating
you can extract the parasitic fater the layout is ready after LVS and DRC. if you use the starRC, you can choose extract the parasitic RC and seperate it with the original netlist, or combine them together.

If it only include the parasitic RC, you need to include the original netlist and the parasitic RC netlist. this is called back annotation. then you can kick off your hspice simulation.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top