how to do post simulation with ncverilog?

[ee_joe]

Hi all,
I want do post simulation with NCVERILOG.
What I have are *.v, *.lib, *.db and *.dspf, here the dspf file is RC parasitics extacted from layout, *.v is gate level netlist.
How to do the post simulation with back annotated dspf file and lib file?
thanks all!

 

[ljxpjpjljx]

do you have SDF file ?'s more convinent for NCVERILOG to read and do post simulation.

 

[asicganesh]

You need SDF + Synthesised netlist

I hope you have the synthesised netlist.

Normally in DC you can generate sdf using write_sdf command.. Mostly a similar instruction should be in RC also.. cross check..

 

[ee_joe]

how does ncverilog work after read SDF file during simulation?

 

[bossbebes]

Hi,

I would like to know what means SCOPE in the SDF file ?

Thxs a lot