How to do part select using parameters in Verilog?

[otis]

I need to do part select using parameters, how can I do that..

for example

parameter config = 3;
parameter flag = 6

reg [31:0] test;

i can use something like this

test = test[falg];

This is OK with bit select

in case if I want to part select what should I do?

will it be ok like this?

parameter jump = "7:4";

output[4:0] = test [jump];

Any recommended method to do part select with parameters?

Thanks!

 

[FvM]

Re: For verilog experts

Using a bitwise assignment like this:

parameter OFFSET = 4;
for (I=0;I<4;I=I+1)
   output[I] = test [I+OFFSET];

 

[otis]

Re: For verilog experts

thanks for the reply.

But I think it would be liitle too much coding in my case..... becasue

As I mentioned earlier i have a 32 bit SFR. ther are 8 different values stored with varied bit length. it is something like this

reg test [31:0];
parameter cnt; //bits positons[3:0]
parameter cfg; //bits positons[9:4]
parameter state; //bits positons[13:10] and so on!


I have use these registers extensively in my code

such as

test [3:0] <= ....

example <= test [9:4]:

So I think it will be lot of "for" loops will be in code.

is there any other technic which make code more elegant

 

[FvM]

Re: For verilog experts

I must admit, that I'm using Verilog only occasionally, when porting IP or on customer request. So I'm not that familiar with the advanced "tricks" tas I'm regarding VHDL. I found however in the lanuguage specification, that there's a construct called indexed part-select, that also allows variable selects. See the examples from IEEE 1364-2005:

big_vect[ 0 +: 8] // == big_vect[ 7 : 0]
big_vect[15 -: 8] // == big_vect[15 : 8]
little_vect[ 0 +: 8] // == little_vect[0 : 7]
little_vect[15 -: 8] // == little_vect[8 :15]
dword[8*sel +: 8] // variable part-select with fixed width

I think, it's clear from the examples, how it works.

 

[otis]

Re: For verilog experts

Hi FvM..thanks for your reply

 

[MrPrezident]

Re: For verilog experts

You could also just use a `define

e.g.

`define JUMP 7:4

output[4:0] = test [`JUMP];

 

[otis]

Re: For verilog experts

This seems to be an elegant way. Thanks for this tip