how to do mixed signal simulation in spectre using netlist?

[Analog_IC]

mixed simulation spectre

thanks

 

[Vamsi Mocherla]

Re: how to do mixed signal simulation in spectre using netli

Do you want to run spectre from console? If that is the case, type the command

spectre yourfile.scs, where yourfile.scs is the netlist you want to run spectre for....

 

[zwei78]

Re: how to do mixed signal simulation in spectre using netli

I am not very clear your mean. But I think if you want to simulation analog netlist and verlog ,you must use the spectreverilog.

 

[altra]

Re: how to do mixed signal simulation in spectre using netli

I also want to know how to run spectreverilog?
could anyone can show me an example.

 

[naisare]

Re: how to do mixed signal simulation in spectre using netli

Some of the verilog models are available in the veriloga library provided by cadence. You can also create your own veriloga models and create the symbol for the model. You can instantiate these symbol in composer and simulate as usual.

 

[Analog_IC]

Re: how to do mixed signal simulation in spectre using netli

hi to all,
i want to know how to use netlist of analog parts with netlist from verilog code which is written for digital parts ... using these netlists can i do mixed signal simulation in artist or someother tool....

I m not talking about using verilog models... i want to use actual circuit (netlist) for simulation.. can i?

help
thanks

 

[Vamsi Mocherla]

Re: how to do mixed signal simulation in spectre using netli

Do you mean the synthesized SPICE netlist from the verilog? If you want to mix SPECTRE and SPICE, you can use the simulator lang=spice option when you start the SPICE netlisting and then shift back to SPECTRE.

 

[zwei78]

Re: how to do mixed signal simulation in spectre using netli

I think you must use spectreverilog to do it . Spectreverilog actually use spectre simulate analog netlist and use verilog-xl simulate verilog file. And you must produce symbol of the verilog block. You must put A-to-D and D-to-A model between analog block and verilog block. This is a mixed signal simulation reference by spectreverilog. It is very detailed.

 

[aaronhor]

It is indeed possible to use spice netlist generated from verilog code and simulate it together with analog blocks. You can create a symbol to represent the spice netlist, modify the CDF parameters, and include the digital cell spice netlist in the model library. Then you can run the simulation. I have found a detail explaination from this link as I am trying to run mixed signal simulation using digital cell spice netlist with analog blocks.

How to include a spice netlist and simulate it in spectre environment | Circuit Design World