How to do mixed-signal simulation in Cadence SpectreVerilog?

[balou3]

mixed-signal simulation

Hello everybody,

I am doing mixed-signal simulation with Cadence SpectreVerilog. I have to apply test vectors to a memory. So, if someone knows: is it possible to use Verilog-XL if arrays are analog and periphery is digital? And, in general, I would like to get more information about mixed-signal simulation with Cadence? :!:

 

[gerryhsu]

Re: mixed-signal simulation

Hello everybody,

I am doing mixed-signal simulation with Cadence SpectreVerilog. I have to apply test vectors to a memory. So, if someone knows: is it possible to use Verilog-XL if arrays are analog and periphery is digital? And, in general, I would like to get more information about mixed-signal simulation with Cadence? :!:

That's what it call mix-mode simulation. Use Dolphin Smash to solve your problem.

 

[balou3]

Re: mixed-signal simulation

Ok, it could be possible to use Dolphin Smash, but how can I use it together with Cadence. The memory cells are designed by Skill, the periphery by Verilog, or it might be I see the problem in wrong way.[align=left] :?

 

[honey]

IS THERE ANY GOOK ON THIS SUBJECT?

 

[gerryhsu]

IS THERE ANY GOOK ON THIS SUBJECT?

Book, you meant? there are a lot on Amazon, but not free

 

[cnspy]

eda and computer books are too expensive.