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How to do memory modeling in Verilog?

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ikru26

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Any one had slides or how to do Memory modeling in verilog..for example SDRAM,DDRAM.LILO and all...any good links are also welcome
 

nand_gates

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Re: Verilog--help

Check source models generated by Synopsys Mempro (outdated now).
I am sure you will learn a lot!
 

jjww110

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Verilog--help

xilinx also provide free memeory model
 

calm

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Verilog--help

some software tools should provide those models, you can check those in your tools package.
 

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