hgby2209
Full Member level 2
verplex lec
I am using verplex lec to do formal check.
I have gating-clock gate level netlist which synthesized by DC+power complier.
But the formal check in RTL vs gate netlist have unmatch points, and when I used non-gating-clock netlist, the formal check was passed.
Could anyone can tell me how to do LEC in RTL vs gating-clock netlist using verplex lec ??
I am using verplex lec to do formal check.
I have gating-clock gate level netlist which synthesized by DC+power complier.
But the formal check in RTL vs gate netlist have unmatch points, and when I used non-gating-clock netlist, the formal check was passed.
Could anyone can tell me how to do LEC in RTL vs gating-clock netlist using verplex lec ??