How to do LEC in RTL vs gating-clock netlist(power compiler)

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verplex lec

I am using verplex lec to do formal check.
I have gating-clock gate level netlist which synthesized by DC+power complier.
But the formal check in RTL vs gate netlist have unmatch points, and when I used non-gating-clock netlist, the formal check was passed.

Could anyone can tell me how to do LEC in RTL vs gating-clock netlist using verplex lec ??
 

gated clock in lec

I have use Verplex to do LEC many times. I think you may have not set right for your netlist. Please check your setting, i think you can pass. Clock gating not affect the LEC.
 

set flatten model verplex

Is it reasonal that the result is different between the dynamic gate-level simulation and the static formal check? In some degree, i think, the answer should be yes.
 

conformal lec clock_gating

I had found out the command to fix this problem.
It is "set flatten model -gated_clock".
 

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